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IRS26302DJ
Switching and Timing Relationships
The relationship between the input and output signals of the IRS26302DJ are illustrated below in Figures 3. From
this figure, we can see the definitions of several timing parameters (i.e., PW IN , PW OUT , t ON , t OFF , t R , and t F ) associated
with this device.
LINx
(or HINx)
50%
PW IN
50%
t ON
t R
PW OUT
t OFF
t F
LOx
(or HOx)
90%
10%
90%
10%
Figure 3: Switching time waveforms
The following two figures illustrate the timing relationships of some of the functionality of the IRS26302DJ; this
functionality is described in further detail later in this document.
During interval A of Figure 5, the HVIC has received the command to turn-on both the high- and low-side switches at
the same time; as a result, the shoot-through protection of the HVIC has prevented this condition and both the high-
and low-side output are held in the off state.
Interval B of Figures 5 and 6 shows that the signal on the ITRIP, GF, PCFtrip input pin has gone from a not active to
an active state; as a result, all of the gate drive outputs have been disabled (i.e., see that HOx has returned to the low
state; LOx is also held low), the voltage on the RCIN pin has been pulled to 0 V, and a fault is reported by the FAULT
output transitioning to the low state. Once the ITRIP, GF, PCFtrip input has returned to the not active state, the
output will remain disabled and the fault condition reported until the voltage on the RCIN pin charges up to V RCIN,TH
(see interval C in Figure 6); the charging characteristics are dictated by the RC network attached to the RCIN pin.
During intervals D and E of Figure 5, we can see that the enable (EN) pin has been pulled low (as is the case when
the driver IC has received a command from the control IC to shutdown); this results in the outputs (HOx and LOx)
being held in the low state until the enable pin is pulled high.
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